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Describe the ESD protection design for pcb layout
29Nov
Jeff コメント件

Describe the ESD protection design for pcb layout

The statIC electricity inside the electronic equipment will cause various damages to the precision semiconductor chip, such as penetrating the thin insulation layer inside the components; Destroy the gate of MOSFET and CMOS components; The trigger in CMOS device is locked; Short circuit reverse bias PN junction; Short circuit positive bias PN junction; Melt the welding wire or aluminum wire inside the active device. In order to eliminate the interference and damage of electrostatic discharge (ESD) to electronic equipment, a variety of technical means need to be taken to prevent.

In the design of pcb board, ESD resistant design can be realized by layering, proper PCB layout and installation. In the design process, most design modifications can be limited to the addition or deletion of components through prediction. ESD can be well prevented by adjusting the layout and wiring. Here are some common precautions.

pcb board

1/multilayer PCB shall be used as far as possible. Compared with double-sided PCB, ground plane and power plane, as well as closely arranged signal line ground wire spacing can reduce common mode impedance and inductive coupling to 1/10 to 1/100 of double-sided PCB. Try to place each signal layer close to a power or ground layer. For high-density pcb with components on the top and bottom surfaces, short connecting lines and many filling grounds, inner layer lines can be considered.

*For double-sided pcb, closely interwoven power and ground grids should be used. The power cord is close to the ground wire, and should be connected as much as possible between the vertical and horizontal lines or the filLED area. The grid size on one side shall be less than or equal to 60mm, and if possible, the grid size shall be less than 13mm.

*Ensure that each circuit is as compact as possible.

*As far as possible, place all connectors aside.

*If possible, lead the power cord in from the center of the card and away from the area that is easily affected by ESD directly.

*On all PCB layers below the connector (easily hit by ESD) leading to the outside of the chassis, place a wide chassis floor or polygon filled floor, and connect them with vias every 13mm.

*Place a mounting hole on the edge of the card, and connect the top and bottom pads of non blocking flux around the mounting hole to the chassis ground.

*During PCB assembly, do not apply any solder on the top or bottom pad. Screws with embedded washers are used to achieve close contact between the pcb and the bracket on the metal chassis/shielding layer or ground plane.

*The same "isolation area" shall be set between the chassis ground and circuit ground of each layer; If possible, keep the interval distance 0.64mm.

*At the top layer and bottom layer of the card near the mounting hole, the chassis ground and circuit ground are connected together with 1.27mm wide wires along the chassis ground wire every 100mm. The bonding pad or mounting hole for installation shall be placed between the chassis ground and the circuit ground adjacent to these connection points. These ground connections can be split with a blade to maintain an open circuit, or jumpered with magnetic beads/high-frequency capacitors.

*If the circuit board will not be put into the metal case or shielding device, the top and bottom case ground wires of the circuit board cannot be coated with solder resist, so that they can be used as the discharge electrode of ESD arc.

*Set a ring ground around the circuit in the following ways:

(1) In addition to the edge connector and chassis ground, a circular path is placed around the entire periphery.

(2) Ensure that the annular ground width of all layers is greater than 2.5mm.

(3) Connect the rings with through holes every 13mm.

(4) The ring ground is connected with the common ground of the multilayer circuit.

(5) For the double-sided board installed in the metal case or shielding device, the ring ground should be connected with the circuit common ground. The unshielded double-sided PCB circuit should be connected to the chassis ground in a ring way, and the ring ground should not be coated with solder resist, so that the ring ground can act as the discharge rod of ESD. At least a 0.5mm wide gap should be placed at a certain position on the ring ground (all layers), so that a large loop can be avoided. The distance between signal wiring and ring ground shall not be less than 0.5mm.

*In the area that can be directly hit by ESD, a ground wire shall be laid near each signal line.

*The I/O circuit shall be as close to the corresponding connector as possible.

*Circuits susceptible to ESD should be placed near the center of the circuit, so that other circuits can provide them with a certain shielding effect.

*Generally, a series resistor and magnetic bead are placed at the receiving end. For cable drivers that are easy to be hit by ESD, a series resistor or magnetic bead can also be placed at the driving end.

*The transient protector is usually placed at the receiving end. Use short and thick lines (less than 5 times the length and preferably less than 3 times the width) to connect to the chassis ground. The signal line and ground wire from the connector shall be directly connected to the transient protector before being connected to other parts of the circuit.

*Filter capacitors shall be placed at the connector or within 25 mm from the receiving circuit.

(1) Use short and thick wires to connect to the chassis ground or the receiving circuit ground (the length is less than 5 times the width, preferably less than 3 times the width).

(2) The signal line and ground wire are connected to the capacitor first and then to the receiving circuit.

*Make sure the signal wire is as short as possible.

*When the length of signal line is greater than 300mm, a ground wire must be laid in parallel.

*Ensure that the loop area between the signal line and the corresponding loop is as SMAll as possible. For long signal lines, the positions of signal lines and ground wires should be changed every few centimeters to reduce the loop area.

*Drive signals from the center of the network into multiple receiving circuits.

*Ensure that the loop area between the power supply and the ground is as small as possible, and place a high-frequency capacitor near each power pin of the integrated circuit chip.

*Place a high-frequency bypass capacitor within 80mm from each connector.

*If possible, fill unused areas with land, and connect the filling ground of all layers every 60mm.

*Make sure to fill the area in any large area (about more than 25mm × 6mm) to the ground.

*When the length of the opening on the power supply or ground plane exceeds 8mm, use narrow wires to connect the two sides of the opening.

*The reset line, interrupt signal line or edge trigger signal line cannot be arranged near the edge of the pcb.

*Connect the mounting holes to the circuit commons or isolate them.

(1) When the metal bracket must be used with the metal shielding device or chassis, a zero ohm resistance shall be used for connection.

(2) Determine the size of the mounting hole to realize the reliable installation of metal or plastic supports. Large pads shall be used on the top and bottom layers of the mounting hole. Solder resistance flux shall not be used on the bottom layer of the bonding pad. Ensure that the bottom layer PCB bonding pad does not use wave soldering process for welding.

*The protected signal lines and unprotected signal lines cannot be arranged in parallel.

*Pay special attention to the wiring of reset, interrupt and control signal lines.

(1) High frequency filtering shall be adopted.

(2) Keep away from input and output circuits.

(3) Keep away from the edge of the circuit board.

*The pcb shall be inserted into the chassis, and shall not be installed at the opening or internal seam.

*Pay attention to PCB wiring under the magnetic bead, between pads, and signal lines that may contact the magnetic bead. Some magnetic beads have good conductivity, which may lead to unexpected conductive paths.

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